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| PT6530 LCD Driver IC DESCRIPTION The PT6530 are 1/3 duty and 1/4 duty LCD display drivers that can directly drive up to 300 segments and can control up to eight general-purpose output ports. These products also incorporate a key scan circuit that accepts input from up to 30 keys to reduce printed circuit board wiring. FEATURES * Key input function for up to 30 keys (A key scan is performed only when a key is pressed.) * 1/3 duty and 1/4 duty drive schemes can be controlled from serial data. * 1/2 bias and 1/3 bias drive schemes can be controlled from serial data. * Capable of driving up to 228 segments using 1/3 duty and up to 300 segments using 1/4 duty. * Sleep mode and all segments off functions that are controlled from serial data. * Segment output port/general-purpose output port function switching that is controlled from serial data. * Serial Interface for clock, Data Input, Data Output, Strobe pins. * Direct display of display data without the use of a decoder provides high generality. * Independent VLCD for the LCD driver block (VLCD can be set to in the range VDD - 0.5 to 6.0V) * Provision of an on-chip voltage-detection type reset circuit prevents incorrect displays. * RES pin provided for forcibly initializing the IC internal circuits. * RC oscillator circuit. APPLICATION * Electronic Equipment with LCD Display BLOCK DIAGRAM Tel: 886-66296288Fax: 886-29174598 http://www.princeton.com.tw2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan PT6530 CONTENTS 1. APPLICATION CIRCUITS ............................................................................................................................................. 3 1.1 1/3 DUTY 1/2 BIAS (FOR NORMAL PANEL USE)............................................................................................... 3 1.2 1/3 DUTY 1/2 BIAS (FOR LARGE PANEL USE) ................................................................................................... 4 1.3 1/3 DUTY 1/3 BIAS (FOR NORMAL PANEL USE)................................................................................................ 5 1.4 1/3 DUTY 1/3 BIAS (FOR LARGE PANEL USE) ................................................................................................... 6 1.5 1/4 DUTY 1/2 BIAS (FOR NORMAL PANEL USE)................................................................................................ 7 1.6 1/4 DUTY 1/2 BIAS (FOR LARGE PANEL USE) ................................................................................................... 8 1.7 1/4 DUTY 1/3 BIAS (FOR NORMAL PANEL USE)................................................................................................ 9 1.8 1/4 DUTY 1/3 BIAS (FOR LARGE PANEL USE) .................................................................................................10 2. ORDER INFORMATION................................................................................................................................................ 11 3 PIN CONFIGURATION ................................................................................................................................................. 11 4. PIN DESCRIPTION ....................................................................................................................................................... 12 5. INPUT/OUPUT CONFIGURATIONS ............................................................................................................................ 13 6. FUNCTION DESCRIPTION .......................................................................................................................................... 14 6.1 SERIAL DATA INPUT ..........................................................................................................................................14 6.2 CONTROL DATA .................................................................................................................................................18 6.3 DISPLAY DATA AND OUTPUT PI CORRESPONDENCE ..................................................................................20 6.4 SERIAL DATA OUTPUT ......................................................................................................................................23 6.5 OUTPUT DATA ....................................................................................................................................................24 6.6 SLEEP MODE ......................................................................................................................................................24 6.7 KEY SCAN OPERATION FUNCTIONS ...............................................................................................................25 6.8 MULTIPLE KEY PRESSES ..................................................................................................................................26 6.9 1/3 DUTY, 1/2 BIAS DRIVE TECHNIQUE ...........................................................................................................27 6.10 1/3 DUTY, 1/3 BIAS DRIVE TECHNIQUE .........................................................................................................28 6.11 1/4 DUTY, 1/2 BIAS DRIVE TECHNIQUE .........................................................................................................29 6.12 1/4 DUTY, 1/3 BIAS DRIVE TECHNIQUE .........................................................................................................30 6.13 VOLTAGE DETECTION TYPE RESET CIRCUIT (VDET) ................................................................................31 6.14 POWER SUPPLY SEQUENCE .........................................................................................................................31 6.15 SYSTEM RESET ................................................................................................................................................31 6.16 NOTE ON TRANSFERRING DISPLAY DATA FROM THE CONTROLLER .....................................................34 6.17 NOTE ON THE CONTROLLER KEY DATA READ TECHNIQUES ..................................................................35 7. ABSOLUTE MAXIMUM RATINGS................................................................................................................................ 38 8. ALLOWABLE OPERATING RANGES .......................................................................................................................... 38 9. ELECTRICAL CHARACTERISTICS ............................................................................................................................. 39 10. PACKAGE INFORMATION ......................................................................................................................................... 41 IMPORTANT NOTICE ....................................................................................................................................................... 42 REVISION HISTORY ......................................................................................................................................................... 43 V1.3 2 June 2010 PT6530 1. APPLICATION CIRCUITS 1.1 1/3 DUTY 1/2 BIAS (FOR NORMAL PANEL USE) Notes: 1. A capacitor can be connected to the power supply line to make the power supply voltage VDD rise time (when power is applied) and the power supply voltage VDD fall time power drops) are at least 1ms when PT6530 is reset via VDET. 2. If the /RES pin is not used to initiate the System Reset Function, it must be connected VDD. 3. The DO pin is an open-drain output and therefore needs a pull-up resistor. This resistor is between 1K and 10K. The value of this resistor must be in accordance with that capacitance of the external wiring so that the signal waveforms are in proper form. V1.3 3 June 2010 PT6530 1.2 1/3 DUTY 1/2 BIAS (FOR LARGE PANEL USE) Notes: 1. A capacitor can be connected to the power supply line to make the power supply voltage VDD rise time (when power is applied) and the power supply voltage VDD fall time power drops) are at least 1ms when PT6530 is reset via VDET. 2. If the /RES pin is not used to initiate the System Reset Function, it must be connected VDD. 3. The DO pin is an open-drain output and therefore needs a pull-up resistor. This resistor is between 1K and 10K. The value of this resistor must be in accordance with that capacitance of the external wiring so that the signal waveforms are in proper form. V1.3 4 June 2010 PT6530 1.3 1/3 DUTY 1/3 BIAS (FOR NORMAL PANEL USE) Notes: 1. A capacitor can be connected to the power supply line to make the power supply voltage VDD rise time (when power is applied) and the power supply voltage VDD fall time power drops) are at least 1ms when PT6530 is reset via VDET. 2. If the /RES pin is not used to initiate the System Reset Function, it must be connected VDD. 3. The DO pin is an open-drain output and therefore needs a pull-up resistor. This resistor is between 1K and 10K. The value of this resistor must be in accordance with that capacitance of the external wiring so that the signal waveforms are in proper form. V1.3 5 June 2010 PT6530 1.4 1/3 DUTY 1/3 BIAS (FOR LARGE PANEL USE) Notes: 1. A capacitor can be connected to the power supply line to make the power supply voltage VDD rise time (when power is applied) and the power supply voltage VDD fall time power drops) are at least 1ms when PT6530 is reset via VDET. 2. If the /RES pin is not used to initiate the System Reset Function, it must be connected VDD. 3. The DO pin is an open-drain output and therefore needs a pull-up resistor. This resistor is between 1K and 10K. The value of this resistor must be in accordance with that capacitance of the external wiring so that the signal waveforms are in proper form. V1.3 6 June 2010 PT6530 1.5 1/4 DUTY 1/2 BIAS (FOR NORMAL PANEL USE) Notes: 1. A capacitor can be connected to the power supply line to make the power supply voltage VDD rise time (when power is applied) and the power supply voltage VDD fall time power drops) are at least 1ms when PT6530 is reset via VDET. 2. If the /RES pin is not used to initiate the System Reset Function, it must be connected VDD. 3. The DO pin is an open-drain output and therefore needs a pull-up resistor. This resistor is between 1K and 10K. The value of this resistor must be in accordance with that capacitance of the external wiring so that the signal waveforms are in proper form. V1.3 7 June 2010 PT6530 1.6 1/4 DUTY 1/2 BIAS (FOR LARGE PANEL USE) Notes: 1. A capacitor can be connected to the power supply line to make the power supply voltage VDD rise time (when power is applied) and the power supply voltage VDD fall time power drops) are at least 1ms when PT6530 is reset via VDET. 2. If the /RES pin is not used to initiate the System Reset Function, it must be connected VDD. 3. The DO pin is an open-drain output and therefore needs a pull-up resistor. This resistor is between 1K and 10K. The value of this resistor must be in accordance with that capacitance of the external wiring so that the signal waveforms are in proper form. V1.3 8 June 2010 PT6530 1.7 1/4 DUTY 1/3 BIAS (FOR NORMAL PANEL USE) Notes: 1 A capacitor can be connected to the power supply line to make the power supply voltage VDD rise time (when power is applied) and the power supply voltage VDD fall time power drops) are at least 1ms when PT6530 is reset via VDET. 2 If the /RES pin is not used to initiate the System Reset Function, it must be connected VDD. 3 The DO pin is an open-drain output and therefore needs a pull-up resistor. This resistor is between 1K and 10K. The value of this resistor must be in accordance with that capacitance of the external wiring so that the signal waveforms are in proper form. V1.3 9 June 2010 PT6530 1.8 1/4 DUTY 1/3 BIAS (FOR LARGE PANEL USE) Notes: 1. A capacitor can be connected to the power supply line to make the power supply voltage VDD rise time (when power is applied) and the power supply voltage VDD fall time power drops) are at least 1ms when PT6530 is reset via VDET. 2. If the /RES pin is not used to initiate the System Reset Function, it must be connected VDD. 3. The DO pin is an open-drain output and therefore needs a pull-up resistor. This resistor is between 1K and 10K. The value of this resistor must be in accordance with that capacitance of the external wiring so that the signal waveforms are in proper form. V1.3 10 June 2010 PT6530 2. ORDER INFORMATION Valid Part Number PT6530 Package Type 100 Pins, LQFP Top Code PT6530-LQ 3 PIN CONFIGURATION V1.3 11 June 2010 PT6530 4. PIN DESCRIPTION Pin Name S1/P1 ~ S8/P8 S9 ~ S73 COM1 COM2 COM3 COM4/S74 I/O Active Handling when unused OPEN Description Segment outputs for displaying the display data transferred by serial data input. The S1/P1 to S8/P8 pins can be used as general-purpose output ports under serial data control. Common driver outputs The frame frequency fo is given by: fo = (fosc/384)Hz. The COM4/S74 pin can be used as a segment output in 1/3 duty. Key scan outputs Although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced CMOS transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. The KS1/S75 and KS2/S76 pins can be used as segment outputs when so specified by the control data. Key scan inputs These pins have built-in pull-down resistors. Oscillator connection An oscillator circuit is formed by connecting an external resistor and capacitor at this pin. Serial data interface connections to the controller. Note that DO, being an open-drain output, requires a pull-up resistor. CE :Chip enable CL :Synchronization clock DI :Transfer data DO :Output data Reset signal input /RES = low.....Display off Key scan disabled All key data is reset to low /RES = high....Display on Key scan enabled However, serial data can be transferred when /RES is low. This pin must be connected to ground. Used for applying the LCD drive 2/3 bias voltage externally. Must be connected to VLCD2 when a 1/2 bias drive scheme is used. Used for applying the LCD drive 1/3 bias voltage externally. Must be connected to VLCD1 when a 1/2 bias drive scheme is used. Logic block power supply connection. Provide a voltage of between 4.5 and 6.0V. LCD driver block power supply connection. Provide a voltage of between VDD -0.5 and 6.0V. Power supply connection. Connect to ground. Pin No. 1~8 9 ~ 73 77 76 75 74 O - O - OPEN KS1/S75 KS2/S76 KS3 ~ KS6 O - OPEN 78 79 80 ~ 83 KI1 ~ KI5 OSC CE CL DI DO I I/O I I I O H H GND VDD 84 ~ 88 95 98 99 100 97 GND OPEN /RES I L VDD 96 TEST VLCD1 VLCD2 VDD VLCD VSS I I I - - OPEN OPEN - 94 91 92 89 90 93 V1.3 12 June 2010 PT6530 5. INPUT/OUPUT CONFIGURATIONS The schematic diagrams of the input and output circuits of the logic section are shown below: INPUT PIN: CL, CE, DI INPUT PIN: KI1 TO KI5 OUTPUT PIN: DO OUTPUT PIN: KS3 TO KS6 OUTPUT PIN: S1/P1 TO S8/P8, S9 TO S73, S75/KS1, S76/KS2 OUTPUT PIN: COM1 TO COM3, COM4/S74 V1.3 13 June 2010 PT6530 6. FUNCTION DESCRIPTION 6.1 SERIAL DATA INPUT 6.1.1 1/3 DUTY WHEN CL IS STOPPED AT THE LOW LEVEL Notes: 1. B0 to B3, A0 to A3 = Serial Interface address 2. DD=Direction Date V1.3 14 June 2010 PT6530 WHEN CL IS STOPPED AT THE HIGH LEVE Notes: 1. B0 to B3, A0 to A3=Serial Interface address 2. DD=Direction Date Serial Interface address: 42H D1 to D228: Display data S0, S1: Sleep control data K0, K1: Key scan output/segment output selection data P0 to P3: Segment output port/general-purpose output port selection data SC: Segment on/off control data DR: 1/2 bias or 1/3 bias drive selection data DT: 1/3 duty or 1/4 duty drive selection data V1.3 15 June 2010 PT6530 6.1.2 1/4 DUTY WHEN CL IS STOPPED AT THE LOW LEVEL Notes: 1. B0 to B3, A0 to A3=Serial Interface address 2. DD=Direction Date V1.3 16 June 2010 PT6530 WHEN CL IS STOPPED AT THE HIGH LEVEL Notes: 1. B0 to B3, A0 to A3=Serial Interface address 2. DD=Direction Date Serial interface address: 42H D1 to D228: Display data S0, S1: Sleep control data K0, k1: Key scan output/segment output selection data P0 to P3: Segment output port/general-purpose output port selection data SC: Segment on/off control data DR: 1/2 bias or 1/3 bias drive selection data DT: 1/3 duty or 1/4 duty drive selection data V1.3 17 June 2010 PT6530 6.2 CONTROL DATA 6.2.1 S0, S1: SLEEP CONTROL DATA These control data bits switch between normal mode and sleep mode and set the states of the KS1 to KS6 key scan outputs during key scan standby. Control Data Segment Outputs Output Pin States During Key Scan Standby Mode OSC Oscillator Common Outputs S0 S1 KS1 KS2 KS3 KS4 KS5 KS6 0 0 Normal Oscillator operating Operating H H H H H H 0 1 Sleep Stopped L L L L L L H 1 0 Sleep Stopped L L L L L H H 1 1 Sleep Stopped L H H H H H H Note: This assumes that the KS1/S75 and KS2/S76 output pins are selected for key scan output. 6.2.2 K0, K1: KEY SCAN OUTPUT/SEGMENT OUTPUT SELECTION DATA These control data bits switch the functions of the KS1/S75 and KS2/S76 output pins between key scan output and segment output. Control Data Output Pin State Maximum Number of Input Keys K0 K1 KS1/S75 KS2/S76 0 0 KS1 KS2 30 0 1 S75 KS2 25 1 X S75 S76 20 Notes: 1. X=Don't care 2. KSn (n=1 or 2): Key scan output 3. Sn (n=75 or 76): Segment output 6.2.3 DT: 1/3 DUTY OR 1/4 DUTY DRIVE SELECTION DATA This control data bit switches between LCD 1/3 duty or 1/4 duty drive. DT Duty Drive Scheme Output Pin State (COM4/S74) 0 1/4 duty drive COM4 1 1/3 duty drive S74 Notes: 1. COM4: Common output 2. S74: Segment output V1.3 18 June 2010 PT6530 6.2.4 P0 TO P3: SEGMENT OUTPUT/GENERAL-PURPOSE OUTPUT PORT SELECTION DATA These control data bits switch the functions of the S1/P1 to S8/P8 output pins between the segment output port and the general-purpose output port. Control Data Output Pin State P0 P1 P2 P3 S1/P1 S2/P2 S3/P3 S4/P4 S5/P5 S6/P6 S7/P7 S8/P8 0 0 0 0 S1 S2 S3 S4 S5 S6 S7 S8 0 0 0 1 P1 S2 S3 S4 S5 S6 S7 S8 0 0 1 0 P1 P2 S3 S4 S5 S6 S7 S8 0 0 1 1 P1 P2 P3 S4 S5 S6 S7 S8 0 1 0 0 P1 P2 P3 P4 S5 S6 S7 S8 0 1 0 1 P1 P2 P3 P4 P5 S6 S7 S8 0 1 1 0 P1 P2 P3 P4 P5 P6 S7 S8 0 1 1 1 P1 P2 P3 P4 P5 P6 P7 S8 1 0 0 0 P1 P2 P3 P4 P5 P6 P7 P8 Notes: 1. Sn (n=1 to 8): Segment output port 2. Pn (n=1 to 8): General-purpose output port The table below lists the correspondence between the display data and the output pins when these pins are selected to be general-purpose output ports. Corresponding Display Data Output Pin 1/3 Duty 1/4 Duty S1/P1 D1 D1 S2/P2 D4 D5 S3/P3 D7 D9 S4/P3 D10 D13 S5/P5 D13 D17 S6/P6 D16 D21 S7/P7 D19 D25 S8/P8 D22 D29 For example, if the circuit is operated in 1/4 duty and the S4/P4 output pin is selected to be a general-purpose output port, the S4/P4 output pin will output a high level (VLCD) when the display data D13 is 1, and will output a low level (Vss) when D13 is 0. 6.2.5 SC: SEGMENT ON/OFF CONTROL DATA This control data bit controls the on/off state of the segments. SC Display State 0 On 1 Off However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. 6.2.6 DR: 1/2 BIAS OR 1/3 BIAS DRIVE SELECTION DATA This control data bit switches between LCD 1/2 bias or 1/3 bias drive. DR Bias Drive Scheme 0 1/3 bias drive 1 1/2 bias drive V1.3 19 June 2010 PT6530 6.3 DISPLAY DATA AND OUTPUT PI CORRESPONDENCE 6.3.1 1/3 DUTY Output Pin S1/P1 S2/P2 S3/P3 S4/P4 S5/P5 S6/P6 S7/P7 S8/P8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 COM1 D1 D4 D7 D10 D13 D16 D19 D22 D25 D28 D31 D34 D37 D40 D43 D46 D49 D52 D55 D58 D61 D64 D67 D70 D73 D76 COM2 D2 D5 D8 D11 D14 D17 D20 D23 D26 D29 D32 D35 D38 D41 D44 D47 D50 D53 D56 D59 D62 D65 D68 D71 D74 D77 COM3 D3 D6 D9 D12 D15 D18 D21 D24 D27 D30 D33 D36 D39 D42 D45 D48 D51 D54 D57 D60 D63 D66 D69 D72 D75 D78 Output Pin S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 COM1 D79 D82 D85 D88 D91 D94 D97 D100 D103 D106 D109 D112 D115 D118 D121 D124 D127 D130 D133 D136 D139 D142 D145 D148 D151 D154 COM2 D80 D83 D86 D89 D92 D95 D98 D101 D104 D107 D110 D113 D116 D119 D122 D125 D128 D131 D134 D137 D140 D143 D146 D149 D152 D155 COM3 D81 D84 D87 D90 D93 D96 D99 D102 D105 D108 D111 D114 D117 D120 D123 D126 D129 D132 D135 D138 D141 D144 D147 D150 D153 D156 Output Pin S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 COM4/S74 KS1/S75 KS2/S76 COM1 D157 D160 D163 D166 D169 D172 D175 D178 D181 D184 D187 D190 D193 D196 D199 D202 D205 D208 D211 D214 D217 D220 D223 D226 COM2 D158 D161 D164 D167 D170 D173 D176 D179 D182 D185 D188 D191 D194 D197 D200 D203 D206 D209 D212 D215 D218 D221 D224 D227 COM3 D159 D162 D165 D168 D171 D174 D177 D180 D183 D186 D189 D192 D195 D198 D201 D204 D207 D210 D213 D216 D219 D222 D225 D228 Note: This is for the case where the output pins S1/P1 to S8/P8, COM4/S74, KS1/S75 and KS2/S76 are selected for use as segment outputs. For example, the table below lists the operation of the S11 segment output pin. Display Data Output Pin State (S11) D31 D32 D33 0 0 0 The LCD segments for COM1, COM2 and COM3 are off. 0 0 1 The LCD segment for COM3 is on. 0 1 0 The LCD segment for COM2 is on. 0 1 1 The LCD segments for COM2 and COM3 are on. 1 0 0 The LCD segment for COM1 is on. 1 0 1 The LCD segments for COM 1 and COM3 are on. 1 1 0 The LCD segments for COM1 and COM2 are on. 1 1 1 The LCD segments for COM1, COM2 and COM3 are on. V1.3 20 June 2010 PT6530 6.3.2 1/4 DUTY Output Pin S1/P1 S2/P2 S3/P3 S4/P4 S5/P5 S6/P6 S7/P7 S8/P8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 COM1 D1 D5 D9 D13 D17 D21 D25 D29 D33 D37 D41 D45 D49 D53 D57 D61 D65 D69 D73 D77 D81 D85 D89 D93 D97 D101 D105 D109 D113 D117 D121 D125 D129 D133 D137 D141 D145 D149 COM2 D2 D6 D10 D14 D18 D22 D26 D30 D34 D38 D42 D46 D50 D54 D58 D62 D66 D70 D74 D78 D82 D86 D90 D94 D98 D102 D106 D110 D114 D118 D122 D126 D130 D134 D138 D142 D146 D150 COM3 D3 D7 D11 D15 D19 D23 D27 D31 D35 D39 D43 D47 D51 D55 D59 D63 D67 D71 D75 D79 D83 D87 D91 D95 D99 D103 D107 D111 D115 D119 D123 D127 D131 D135 D139 D143 D147 D151 COM4 D4 D8 D12 D16 D20 D24 D28 D32 D36 D40 D44 D48 D52 D56 D60 D64 D68 D72 D76 D80 D84 D88 D92 D96 D100 D104 D108 D112 D116 D120 D124 D128 D132 D136 D140 D144 D148 D152 Output Pin S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 KS1/S75 KS2/S76 COM1 D153 D157 D161 D165 D169 D173 D177 D181 D185 D189 D193 D197 D201 D205 D209 D213 D217 D221 D225 D229 D233 D237 D241 D245 D249 D453 D257 D261 D265 D269 D273 D277 D281 D285 D289 D293 D297 COM2 D154 D158 D162 D166 D170 D174 D178 D182 D186 D190 D194 D198 D202 D206 D210 D214 D218 D222 D226 D230 D234 D238 D242 D246 D250 D254 D258 D262 D266 D270 D274 D278 D282 D286 D290 D294 D298 COM3 D155 D159 D163 D167 D171 D175 D179 D183 D187 D191 D195 D199 D203 D207 D211 D215 D219 D223 D227 D231 D235 D239 D243 D247 D251 D255 D259 D263 D267 D271 D275 D279 D283 D287 D291 D295 D299 COM4 D156 D160 D164 D168 D172 D176 D180 D184 D188 D192 D196 D200 D204 D208 D212 D216 D220 D224 D228 D232 D236 D240 D244 D248 D252 D256 D260 D264 D268 D272 D276 D280 D284 D288 D292 D296 D300 Note: This is for the case where the output pins S1/P1 to S8/P8, KS1/S75 and KS2/S76 are selected for use as segment outputs. V1.3 21 June 2010 PT6530 For example, the table below lists the segment output states for the S11 output pin. Display Data Output Pin State (S11) D41 D42 D43 D44 0 0 0 0 The LCD segment for COM1, COM2, COM3 and COM4 are off. 0 0 0 1 The LCD segment for COM4 is on. 0 0 1 0 The LCD segment for COM3 is on. 0 0 1 1 The LCD segments for COM3 and COM4 are on. 0 1 0 0 The LCD segment for COM2 is on. 0 1 0 1 The LCD segments for COM2 and COM4 are on. 0 1 1 0 The LCD segments for COM2 and COM3 are on. 0 1 1 1 The LCD segments for COM2, COM3 and COM4 are on. 1 0 0 0 The LCD segment for COM1 is on. 1 0 0 1 The LCD segments for COM1 and COM4 are on. 1 0 1 0 The LCD segments for COM1 and COM3 are on. 1 0 1 1 The LCD segments for COM1, COM3 and COM4 are on. 1 1 0 0 The LCD segments for COM1 and COM2 are on. 1 1 0 1 The LCD segments for COM1, COM2 and COM4 are on. 1 1 1 0 The LCD segments for COM1, COM2 and COM3 are on. 1 1 1 1 The LCD segments for COM1, COM2,COM3 and COM4 are on. V1.3 22 June 2010 PT6530 6.4 SERIAL DATA OUTPUT WHEN CL IS STOPPED AT THE LOW LEVEL Notes: 1. X=Don't care 2. B0 to B3, A0 to A3: Serial Interface address WHEN CL IS STOPPED AT THE HIGH LEVEL Notes: 1. X=Don't care 2. B0 to B3, A0 to A3: Serial Interface address 3. Serial Interface address: 43H 4. KD1 to KD30: Key data 5. SA: Sleep acknowledge data 6. If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid. V1.3 23 June 2010 PT6530 6.5 OUTPUT DATA 6.5.1 KD1 TO KD30: KEY DATA When a key matrix of up to 30 keys is formed from the KS1 to KS6 output pins and the KI1 to KI5 input pins and one of those keys is pressed, the key output data corresponding to that key will be set to 1. The table shows the relationship between those pins and the key data bits. Item KI1 KI2 KI3 KI4 KI5 KS1/S75 KD1 KD2 KD3 KD4 KD5 KS2/S76 KD6 KD7 KD8 KD9 KD10 KS3 KD11 KD12 KD13 KD14 KD15 KS4 KD16 KD17 KD18 KD19 KD20 KS5 KD21 KD22 KD23 KD24 KD25 KS6 KD26 KD27 KD28 KD29 KD30 When the KS1/S75 and KS2/S76 output pins are selected to be segment outputs by control data bits K0 and K1 and a key matrix of up to 20 keys is formed using the KS3 to KS6 output pins and the KI1 to KI5 input pins, the KD1 to KD10 key data bits will be set to 0. 6.5.2 SA: SLEEP ACKNOWLEDGE DATA This output data is set to the state when the key was pressed. In that case DO will go to the low level. If serial data is input during this period and the mode is set (normal mode or sleep mode), the IC will be set to that mode. SA is set to 1 in the sleep mode and to 0 in the normal mode. 6.6 SLEEP MODE Sleep mode is set up by setting S0 or S1 in the control data to 1. The segment outputs will all go low and the common outputs will also go low, and the oscillator on the OSC pin will stop (it will be started by a key press). This reduces power dissipation. This mode is cleared by sending control data with both S0 and S1 set to 0. However, note that the S1/P1 to S8/P8 outputs can be used as general-purpose output ports according to the state of the P0 to P3 control data bits, even in sleep mode. (See the control data description for details.) V1.3 24 June 2010 PT6530 6.7 KEY SCAN OPERATION FUNCTIONS 6.7.1 KEY SCAN TIMING The key scan period is 288T(s). To reliably determine the on/off state of the keys, the PT6530 scans the keys twice and determines that a key has been pressed when the key data agrees. It outputs a key data read request (a low level on DO) 615T(s) after starting a key scan. If the key data does not agree and a key was pressed at that point, it scans the keys again. Thus the PT6530 cannot detect a key press shorter than 615T(s). Note: *: In sleep mode the high/low state of these pins is determined by the S0 and S1 bits in the control data. Key scan output signals are not output from pins that are set low. 6.7.2 IN NORMAL MODE * The pins KS1 to KS6 are set high. * When a key is pressed a key scan is started and the keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. * If a key is pressed for longer than 615T(s) (Where T= 1 ) the PT6530 outputs a key data read request (a low fosc level on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high. After the controller reads the key data, the key data read request is cleared (DO is set high) and the PT6530 performs another key scan. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 and 10K). V1.3 25 June 2010 PT6530 6.7.3 IN SLEEP MODE * The pins KS1 to KS6 are set to high or low by the S0 and S1 bits in the control data. (See the control data description for details.) * If a key on one of the lines corresponding to a KS1 to KS6 pin which is set high is pressed, the oscillator on the OSC pin is started and a key scan is performed. Keys are scanned until all keys are released. Multiple key presses are recognized by determining whether multiple key data bits are set. * If a key is pressed for longer than 615T(s)(Where T= 1 ) the PT6530 outputs a key data read request (a low level fosc on DO) to the controller. The controller acknowledges this request and reads the key data. However, if CE is high during a serial data transfer, DO will be set high. * After the controller reads the key data, the key data read request is cleared (DO is set high) and the PT6530 performs another key scan. However, this does not clear sleep mode. Also note that DO, being an open-drain output, requires a pull-up resistor (between 1 and 10K). * Sleep mode key scan example Example: S0=0, S1=1 (sleep with only KS6 high) Note: *: These diodes are required to reliable recognize multiple key presses on the KS6 line when sleep mode state with only KS6 high, as in the above example. That is, these diodes prevent incorrect operations due to sneak currents in the KS6 key scan output signal when keys on the KS1 to KS5 lines are pressed at the same time. 6.8 MULTIPLE KEY PRESSES Although the PT6530 is capable of key scanning without inserting diodes for dual key presses, triple key presses on the KI1 to KI5 input pin lines, or multiple key presses on the KS1 to KS6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. Therefore, a diode must be inserted in series with each key. Applications that do not recognize multiple key presses of three or more keys should check the key data for three or more 1 bit and ignore such data. V1.3 26 June 2010 PT6530 6.9 1/3 DUTY, 1/2 BIAS DRIVE TECHNIQUE V1.3 27 June 2010 PT6530 6.10 1/3 DUTY, 1/3 BIAS DRIVE TECHNIQUE V1.3 28 June 2010 PT6530 6.11 1/4 DUTY, 1/2 BIAS DRIVE TECHNIQUE V1.3 29 June 2010 PT6530 6.12 1/4 DUTY, 1/3 BIAS DRIVE TECHNIQUE V1.3 30 June 2010 PT6530 6.13 VOLTAGE DETECTION TYPE RESET CIRCUIT (VDET) This circuit generates an output signal and resets the system when logic block power is first applied and when the voltage drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage VDET, which is 2.3V, typical. To assure that this function operates reliably, a capacitor must be added to the logic block power supply line so that the logic block power supply voltage VDD rise time when the logic block power is first applied and the logic block power supply voltage VDD fall time when the voltage drops are both at least 1ms. (see Figure 1 and Figure 2.) 6.14 POWER SUPPLY SEQUENCE The following sequences must be observed when power is turned on and off. (see Figure 1 and Figure 2.) * Power on: Logic block power supply(VDD) on LCD driver block power supply(VLCD) on. * Power off: LCD driver block power supply(VLCD) off Logic block power supply(VDD) off. However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off at the same time. 6.15 SYSTEM RESET The PT6530 supports the reset methods described below. When a system reset is applied, display is turned off, key scanning is stopped, and all the key data is reset to low. When the reset is cleared, display is turned on and key scanning become possible. 6.15.1 RESET METHODS (1) Reset at power-on and power-down If at least 1ms is assured as the logic block supply voltage VDD rise time when logic block power is applied, a system reset will be applied by the VDET output signal when the logic block supply voltage is brought up. If at least 1ms is assured as the logic block supply voltage VDD fall time when logic block power drops, a system reset will be applied in the same manner by the VDET output signal when the supply voltage is lowered. Note that the reset is cleared at the point when all the serial data (1/3 duty: the display data D1 to D228 and the control data, 1/4 duty: the display data D1 to D300 and the control data) has been transferred, i.e., on the fall of the CE signal on the transfer of the last direction data, after all the direction data has been transferred. However, the above operations will be performed regardless of the state (high or low) of the /RES pin. If /RES is high, the reset will be cleared at the point the above operations are completed. On the other hand, if /RES is low, the system will remain in the reset period as long as /RES is not set high, even if the above operations are completed. (see Figure 1 and Figure 2.) (2) Reset when the logic block power supply voltage is in the allowable operating range (VDD=3.0 to 6.0V). The system is reset when the /RES pin is set low, and the reset is cleared by setting /RES pin high. V1.3 31 June 2010 PT6530 1/3 DUTY Figure 1 1/4 DUTY Figure 2 V1.3 32 June 2010 PT6530 6.15.2 PT6530 INTERNAL BLOCK STATES DURING THE RESET PERIOD * Clock Generator Reset is applied and the base clock is stopped. However, the OSC pin state (normal or sleep mode) is determined after the S0 and S1 control data bits are transferred. * Common Diver, Segment Driver & Latch Reset is applied and the display is turned off. However, display data can be input to the latch circuit in this state. * Key Scan Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is disabled. * Key Buffer Reset is applied and all the key data is set to low. * Serial Interface, Control Register, Shift Register Block that are reset V1.3 33 June 2010 PT6530 6.15.3 OUTPUT PIN STATES DURING THE RESET PERIOD Output Pin S1/P1 to S8/P8 S9 to S73 COM1 to COM3 COM4/S74 KS1/S75. KS2/S76 KS3 to KS5 KS6 DO State During Reset L (Note 2) L L L (Note 3) L (Note 2) X (Note 4) H H (Note 5) Notes: 1. X = Don't care 2. These output pins are forcibly set to the segment output function and held low. 3. When power is first applied, this output pin is forcibly set to the common output function and held low. However, when the DT control data bit is transferred, either the common output or the segment output function is selected. 4. When power is first applied, these output pins are undefined until the S0 and S1 control data bits have been transferred. 5. Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10K is required. This pin remains high during the reset period even if a key data read operation is performed. 6.16 NOTE ON TRANSFERRING DISPLAY DATA FROM THE CONTROLLER When using the PT6530 in 1/3 duty, applications transfer the display data (D1 to D228) in three operations, and in 1/4 duty, they transfer the display data (D1 to D300) in four operations. In either case, applications should transfer all of the display data within 30ms to maintain the quality of the displayed image. V1.3 34 June 2010 PT6530 6.17 NOTE ON THE CONTROLLER KEY DATA READ TECHNIQUES 6.17.1 TIMER BASED KEY DATA ACQUISITION FLOWCHART TIMING CHART t5: Key scan execution time when the key data agreed for two key scans. (615T(s)) t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1230T(s)) t7: Key address (43H) transfer time T = t8: Key data read time 1 fosc EXPLANATION In this technique, the controller uses a timer to determine key on/off states and read the key data. The controller must check the DO state when CE is low every t9 period without fail. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. The period t9 in this technique must satisfy the following condition. t9>t6+t7+t8 If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid. V1.3 35 June 2010 PT6530 6.17.2 INTERRUPT BASED KEY DATA ACQUISITION FLOWCHART TIMING CHART t5: Key scan execution time when the key data agreed for two key scans. (615T(s)) t6: Key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (1230T(s)) t7: Key address (43H) transfer time T = 1 fosc t8: Key data read time V1.3 36 June 2010 PT6530 EXPLANATION In this technique, the controller uses interrupts to determine key on/off states and read the key data. The controller must check the DO state when CE is low. If DO is low, the controller recognizes that a key has been pressed and executes the key data read operation. After that the next key on/off determination is performed after the time t10 has elapsed by checking the DO state when CE is low and reading the key data. The period t10 in this technique must satisfy the following condition. t10 > t6 If a key data read operation is executed when DO is high, the read key data (KD1 to KD30) and sleep acknowledge data (SA) will be invalid. V1.3 37 June 2010 PT6530 7. ABSOLUTE MAXIMUM RATINGS (VSS=0V, Ta=25) Parameter Maximum Supply Voltage Input Voltage Symbol VDD max VLCD max VIN1 VIN2 VIN3 VOUT1 VOUT2 VOUT3 IOUT1 IOUT2 IOUT3 IOUT4 Pd max Topr Tstg Condition VDD VLCD CE, CL, DI, /RES OSC, TEST VLCD1, VLCD2, KI1 to KI5 DO OSC S1 to S76, COM1 to COM4, KS1 to KS6, P1 to P8 S1 to S76 COM1 to COM4 KS1 to KS6 P1 to P8 Ta = 85 Rating -0.3 ~ +7.0 -0.3 ~ +7.0 -0.3 ~ VDD+0.3 -0.3 ~ VDD+0.3 -0.3 ~ VLCD+0.3 -0.3 ~ VDD+0.3 -0.3 ~ VDD+0.3 -0.3 ~ VLCD+0.3 300 3 1 5 200 -40 ~ +85 -65 ~ +150 A mA mW Unit V V Output Voltage V Output Current Allowable Power Dissipation Operating Temperature Storage Temperature 8. ALLOWABLE OPERATING RANGES (Ta=-40 to +85, VSS=0V) Parameter Supply Voltage Input Voltage Input High-Level Voltage Input Low Level Voltage Recommended External Resistance Recommended External Capacitance Guaranteed Oscillator Range Data Setup Time Data Hold Time CE Wait Time CE Setup Time CE Hold Time High Level Clock Pulse Width Low Level Clock Pulse Width Rise Time Fall Time DO Output Delay Time DO Rise Time Symbol VDD VLCD VLCD1 VLCD2 VIH1 VIH2 VIL ROSC COSC fosc tds tdh tcp tcs tch tH tL tr tf tdc tdr Condition VDD VLCD VLCD1 VLCD2 CE, CL, DI, /RES KI1 to KI5 CE, CL, DI, /RES, (KI1 to KI5) OSC OSC OSC CL,DI: Figure 4 CL, DI: Figure 4 CE, CL: Figure 4 CE, CL: Figure 4 CE, CL: Figure 4 CL: Figure 4 CL: Figure 4 CE, CL, DI: Figure 4 CE, CL, DI: Figure 4 DO, RPU=4.7K, CL=10pf (see note): Figure 4 DO, RPU=4.7K, CL=10pf (see note): Figure 4 Min 3 VDD-0.5 0.8 VDD 0.6 VLCD 0 19 160 160 160 160 160 160 160 Typ 2/3VLCD 1/3VLCD 39 1000 38 160 160 Max 6.0 6.0 VLCD VLCD VDD VLCD 0.2 VDD (0.2VLCD) 76 1.5 1.5 Unit V V V V V V V K pF KHz ns ns ns ns ns ns ns ns ns s s Note: Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor RPU and the load capacitance CL. V1.3 38 June 2010 PT6530 9. ELECTRICAL CHARACTERISTICS Parameter Hysteresis Power-down Detection Voltage Input High level Current Input Low Level Current Input Floating Voltage Pull-down Resistance Output Off Leakage Current Output High Level Voltage Symbol VH VDET IIH IIL VIF RPD IOFFH VOH1 VOH2 VOH3 VOH4 VOL1 VOL2 VOL3 VOL4 VOL5 VMID1 Output Middle Level Voltage (see note) VMID2 VMID3 VMID4 VMID5 Oscillator Frequency fosc IDD1 IDD2 Current Drain ILCD1 ILCD2 ILCD3 CE, CL, DI, /RES: VI=VDD CE, CL, DI, /RES: VI=0V KI1 to KI5 KI1 to KI5: VLCD=5.0V DO: VO=6.0V KS1 to KS6: IO=-500A P1 to P8: IO=-1mA S1 to S76: IO=-20A COM1 to COM4: IO=-100A KS1 to KS6: IO=25A P1 to P8: IO=1mA S1 to S76: IO=20A COM1 to COM4: IO=100A DO: IO=1mA COM1 to COM4: 1/2 bias, IO=100A S1 to S76: 1/3 bias, IO=20A S1 to S76: 1/3 bias, IO=20A COM1 to COM4: 1/3 bias, IO=100A COM1 to COM4: 1/3 bias, IO=100A OSC: Rosc=39K, Cosc=1000pF VDD: Sleep mode VDD: VDD=6.0V. output open, fosc=38KHz VLCD: Sleep mode VLCD: VLCD=6.0V, output open, 1/2 bias, fosc=38KHz VLCD: VLCD=6.0V, output open, 1/3 bias, fosc=38KHz VLCD-1.0 VLCD-1.0 VLCD-1.0 VLCD-1.0 0.2 VLCD-0.5 -5.0 50 100 0.05VLCD 250 6.0 VLCD-0.2 V 0.5 1.5 1.0 1.0 1.0 0.5 1/2VLCD+1.0 2/3VLCD+1.0 1/3VLCD+1.0 2/3VLCD+1.0 1/3VLCD+1.0 38 270 200 120 45.6 100 540 5 400 240 A KHz V Conditions CE, CL, DI, /RES (KI1 to KI5) Min. Typ. 0.1VDD (0.1VLCD) 2.2 Max. Unit V 2.6 5.0 V A A V K A 1.8 Output Low Level Voltage V 0.1 1/2VLCD-1.0 2/3VLCD-1.0 1/3VLCD-1.0 2/3VLCD-1.0 1/3VLCD-1.0 30.4 Note: Excluding the bias voltage generation divider resistor built into VLCD1 and VLCD2. (See Figure 3) Figure 3 V1.3 39 June 2010 PT6530 WHEN CL IS STOPPED AT THE LOW LEVEL WHEN CL IS STOPPED AT THE HIGH LEVEL Figure 4 V1.3 40 June 2010 PT6530 10. PACKAGE INFORMATION 100 PINS, LQFP Symbol A A1 A2 b c D D1 E E1 e L1 Notes: 1. All controlling dimensions are in millimeters. 2. Refer to JEDEC MS-026BED Min. 0.05 1.35 0.17 0.09 0 Nom. 1.40 0.22 16.00 BSC 14.00 BSC 16.00 BSC 14.00 BSC 0.50 BSC 1.00 REF 3.5 Max. 1.60 0.15 1.45 0.27 0.20 7 V1.3 41 June 2010 PT6530 IMPORTANT NOTICE Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw V1.3 42 June 2010 |
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